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| Dual 160 MHz Rail-to-Rail Amplifier AD8042 FEATURES Single AD8041 and Quad AD8044 also Available Fully Specified at +3 V, +5 V, and 5 V Supplies Output Swings to Within 30 mV of Either Rail Input Voltage Range Extends 200 mV Below Ground No Phase Reversal with Inputs 0.5 V Beyond Supplies Low Power of 5.2 mA per Amplifier High Speed and Fast Settling on 5 V: 160 MHz -3 dB Bandwidth (G = +1) 200 V/ s Slew Rate 39 ns Settling Time to 0.1% Good Video Specifications (RL = 150 , G = +2) Gain Flatness of 0.1 dB to 14 MHz 0.02% Differential Gain Error 0.04 Differential Phase Error Low Distortion -64 dBc Worst Harmonic @ 10 MHz Drives 50 mA 0.5 V from Supply Rails APPLICATIONS Video Switchers Distribution Amplifiers A/D Driver Professional Cameras CCD Imaging Systems Ultrasound Equipment (Multichannel) PRODUCT DESCRIPTION CONNECTION DIAGRAM 8-Lead Plastic DIP and SOIC 1 2 3 4 8 7 6 +VS OUT2 -IN2 +IN2 OUT1 -IN1 +IN1 -VS AD8042 5 The output voltage swing extends to within 30 mV of each rail, providing the maximum output dynamic range. Additionally, it features gain flatness of 0.1 dB to 14 MHz while offering differential gain and phase error of 0.04% and 0.06 on a single 5 V supply. This makes the AD8042 useful for professional video electronics such as cameras, video switchers, or any high speed portable equipment. The AD8042's low distortion and fast settling make it ideal for buffering single supply, high speed A/D converters. The AD8042 offers low power supply current of 12 mA max and can run on a single 3.3 V power supply. These features are ideally suited for portable and battery-powered applications where size and power are critical. The wide bandwidth of 160 MHz along with 200 V/ms of slew rate on a single 5 V supply make the AD8042 useful in many generalpurpose, high speed applications where single supplies from 3.3 V to 12 V and dual power supplies of up to 6 V are needed. The AD8042 is available in 8-lead plastic DIP and SOIC. 15 12 9 CLOSED-LOOP GAIN (dB) The AD8042 is a low power voltage feedback, high speed amplifier designed to operate on +3 V, +5 V, or 5 V supplies. It has true single supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail. VS = 5V G = +1 CL = 5pF RL = 2k TO 2.5V 5V G=1 RL = 2k TO +2.5V 6 3 0 -3 -6 -9 2.5V 0V -12 1V 1s -15 1 10 FREQUENCY (MHz) 100 500 Figure 1. Output Swing: Gain = -1, VS = +5 V Figure 2. Frequency Response REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD8042-SPECIFICATIONS (@T = 25 C, V = 5 V, R = 2 k A S L to 2.5 V, unless otherwise noted.) AD8042 Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst-Case Crosstalk DC PERFORMANCE Input Offset Voltage Conditions G = +1 G = +2, RL = 150 W, RF = 200 W G = -1, VO = 2 V Step VO = 2 V p-p G = -1, VO = 2 V Step Min 125 130 Typ 160 14 200 30 26 39 -73 15 700 0.04 0.04 0.06 0.24 -63 3 Max Unit MHz MHz V/ms MHz ns ns dB nV//Hz fA//Hz % % Degrees Degrees dB mV mV mV/C mA mA mA dB dB kW pF V dB V V V mA mA mA pF fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kW f = 10 kHz f = 10 kHz G = +2, RL = 150 W to 2.5 V G = +2, RL = 75 W to 2.5 V G = +2, RL = 150 W to 2.5 V G = +2, RL = 75 W to 2.5 V f = 5 MHz, RL = 150 W to 2.5 V 0.06 0.12 TMIN to TMAX Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing: Output Voltage Swing: Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Specifications subject to change without notice. 9 12 3.2 4.8 0.5 12 1.2 0.2 100 90 300 1.5 -0.2 to +4 74 RL = 1 kW TMIN to TMAX 90 VCM = 0 V to 3.5 V RL = 10 kW to 2.5 V RL = 1 kW to 2.5 V RL = 50 W to 2.5 V TMIN to TMAX, VOUT = 0.5 V to 4.5 V Sourcing Sinking G = +1 68 0.03 to 4.97 0.10 to 4.9 0.05 to 4.95 0.4 to 4.4 0.36 to 4.45 50 90 100 20 3 12 6.4 +85 VS- = 0 V to -1 V, or VS+ = +5 V to +6 V 72 -40 5.5 80 V mA dB C -2- REV. C AD8042 SPECIFICATIONS (@T = 25 C, V = 5 V, R = 2 k A S L to 1.5 V, unless otherwise noted.) Min 120 120 AD8042 Typ 140 11 170 25 30 45 -56 16 500 0.10 0.10 0.12 0.27 -68 3 9 12 3.2 4.8 0.6 Max Unit MHz MHz V/ms MHz ns ns dB nV//Hz fA//Hz % % Degrees Degrees dB mV mV mV/C mA mA mA dB dB kW pF V dB V V V mA mA mA pF 12 6.4 70 V mA dB C Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst-Case Crosstalk DC PERFORMANCE Input Offset Voltage Conditions G = +1 G = +2, RL = 150 W, RF = 200 W G = -1, VO = 2 V Step VO = 2 V p-p G = -1, VO = 1 V Step fC = 5 MHz, VO = 2 V p-p, G = -1, RL = 100 W f = 10 kHz f = 10 kHz G = +2, RL = 150 W to 1.5 V, Input VCM = 1 V RL = 75 W to 1.5 V, Input VCM = 1 V G = +2, RL = 150 W to 1.5 V, Input VCM = 1 V RL = 75 W to 1.5 V, Input VCM = 1 V f = 5 MHz, RL = 1 kW to 1.5 V TMIN to TMAX Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing: Output Voltage Swing: Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Specifications subject to change without notice. 12 1.2 0.2 100 90 300 1.5 -0.2 to +2 74 0.03 to 2.97 0.05 to 2.95 0.25 to 2.65 50 50 70 17 RL = 1 kW TMIN to TMAX 90 VCM = 0 V to 1.5 V RL = 10 kW to 1.5 V RL = 1 kW to 1.5 V RL = 50 W to 1.5 V TMIN to TMAX, VOUT = 0.5 V to 2.5 V Sourcing Sinking G = +1 66 0.1 to 2.9 0.3 to 2.6 3 VS- = 0 V to -1 V, or VS+ = +3 V to +4 V 68 0 5.5 80 REV. C -3- AD8042 SPECIFICATIONS (@T = 25 C, V = A S 5 V, RL = 2 k to 0 V, unless otherwise noted.) Min 125 145 AD8042 Typ Max 170 18 225 35 22 32 -78 15 700 0.02 0.02 0.04 0.12 -63 3 Unit MHz MHz V/ms MHz ns ns dB nV//Hz fA//Hz % % Degrees Degrees dB mV mV mV/C mA mA mA dB dB kW pF V dB V V V mA mA mA pF V mA dB C Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst-Case Crosstalk DC PERFORMANCE Input Offset Voltage Conditions G = +1 G = +2, RL = 150 W, RF = 200 W G = -1, VO = 2 V Step VO = 2 V p-p G = -1, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kW f = 10 kHz f = 10 kHz G = +2, RL = 150 W G = +2, RL = 75 W G = +2, RL = 150 W G = +2, RL = 75 W f = 5 MHz, RL = 150 W 0.05 0.10 TMIN to TMAX Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing Output Voltage Swing Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Specifications subject to change without notice. 9.8 14 3.2 4.8 0.6 12 1.2 0.2 94 86 300 1.5 -5.2 to +4 74 RL = 1 kW TMIN to TMAX 90 VCM = -5 V to +3.5 V RL = 10 kW RL = 1 kW RL = 50 W TMIN to TMAX, VOUT = -4.5 V to +4.5 V Sourcing Sinking G = +1 66 -4.97 to +4.97 -4.8 to +4.8 -4.9 to +4.9 -4 to +3.2 -4.2 to +3.5 50 100 100 25 3 12 7 +85 VS- = -5 V to -6 V, or VS+ = +5 V to +6 V 68 -40 6 80 -4- REV. C AD8042 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION (W) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . 1.3 W Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.9 W Input Voltage (Common Mode) . . . . . . . . . . . . . VS 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 3.4 V Output Short-Circuit Duration Observe Power Derating Curves Storage Temperature Range (N, R) . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air: 8-Lead Plastic DIP Package: qJA = 90C/W 8-Lead SOIC Package: qJA = 155C/W While the AD8042 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 8-LEAD PLASTIC-DIP PACKAGE TJ = 150 C 1.5 1.0 8-LEAD SOIC PACKAGE 0.5 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE ( C) 70 80 90 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8042 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic--approximately 150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. Figure 3. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8042AN AD8042AR AD8042AR-REEL AD8042AR-REEL7 AD8042ARZ* AD8042ARZ-REEL* AD8042ARZ-REEL7* AD8042ACHIPS *Z = Pb-free part Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead DIP 8-Lead SOIC 8-Lead SOIC 13" REEL 8-Lead SOIC 7" REEL 8-Lead SOIC 8-Lead SOIC 13" REEL 8-Lead SOIC 7" REEL DIE Package Option N-8 SO-8 SO-8 SO-8 SO-8 SO-8 SO-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4,000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8042 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C -5- AD8042-Typical Performance Characteristics 100 90 80 70 VS = 5V T = 25 C 140 PARTS, SIDE A & B MEAN = -1.52mV STD DEVIATION = 1.15 SAMPLE SIZE = 280 (140 AD8042S) 100 95 OPEN-LOOP GAIN (dB) 90 FREQUENCY 60 50 40 30 20 10 0 -6 -5 -4 -3 -2 -1 0 1 VOS (mV) 85 VS = 5V T = 25 C 80 75 2 3 4 5 6 70 0 250 500 750 1000 1250 1500 LOAD RESISTANCE ( ) 1750 2000 TPC 1. Typical Distribution of VOS TPC 4. Open-Loop Gain vs. RL to 2.5 V 30 VS = 5V MEAN = -12.6 V/ C STD DEV = 2.02 V/ C SAMPLE SIZE = 60 100 98 VS = 5V RL = 1k 25 20 FREQUENCY OPEN-LOOP GAIN (dB) 96 94 15 92 90 10 5 88 0 -18 -16 -14 -12 -10 -8 -6 VOS DRIFT( V/ C) -4 -2 0 86 -40 -20 0 20 40 TEMPERATURE ( C) 60 80 TPC 2. VOS Drift Over -40C to +85C TPC 5. Open-Loop Gain vs. Temperature 0 100 -0.2 VS = 5V VCM = 0V 90 RL = 500 TO 2.5V VS = 5V INPUT BIAS CURRENT ( A) -0.4 OPEN-LOOP GAIN (dB) -0.6 -0.8 -1 -1.2 -1.4 -1.6 80 RL = 50 70 TO 2.5V 60 50 -1.8 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 40 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE (V) 4 4.5 5 TEMPERATURE( C) TPC 3. IB vs. Temperature TPC 6. Open-Loop Gain vs. Output Voltage -6- REV. C AD8042 0.04 NTSC Subcarrier (3.579 MHz) 300 INPUT VOLTAGE NOISE (nV/ Hz) 100 30 10 3 1 DIFFERENTIAL GAIN ERROR (%) 0.03 0.02 0.01 0.00 -0.01 0.05 VS = 5V G = +2 RL = 150 TO 2.5V VS = 5V G = +2 RL = 150 DIFFERENTIAL PHASE ERROR (deg) 0.04 0.03 0.02 0.01 0 -0.01 0 VS = 5V G = +2 RL = 150 TO 2.5V VS = 5V G = +2 RL = 150 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 10 20 30 40 50 60 70 80 MODULATING RAMP LEVEL (IRE) 90 100 TPC 7. Input Voltage Noise vs. Frequency TPC 10. Differential Gain and Phase Errors -30 -40 -50 -60 VS = 5V, AV = 2, RL = 100 TO 2.5V VS = 5V, AV = 1, RL = 100 TO 2.5V VS = 3V, AV = -1, RL = 100 TO 1.5V 0.6 0.5 0.4 VS = 5V G = +2 RF = 200 RL = 150 TOTAL HARMONIC DISTORTION (dBc) TO 2.5V NORMALIZED GAIN (dB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 14MHz -70 -80 -90 VS = 5V, AV = 1, RL = 1k TO 2.5V 1 VS = 5V, AV = 2, RL = 1k TO 2.5V -100 3 2 4 5 6 FUNDAMENTAL FREQUENCY (MHz) 7 8 9 10 1 10 FREQUENCY (MHz) 100 500 TPC 8. Total Harmonic Distortion TPC 11. 0.1 dB Gain Flatness -30 -40 120 100 10MHz 80 VS = 5V G = +2 RF = 200 RL = 150 GAIN WORST HARMONIC (dBc) OPEN-LOOP GAIN (dB) -50 -60 TO 2.5V 45 60 40 20 0 5MHz -70 -80 1MHz -90 -100 -110 0.0 VS = 5V, G = +2, RL = 1k TO 2.5V -45 -90 PHASE -135 -180 -225 0.1 1 10 FREQUENCY (MHz) 100 -270 500 -20 -40 -60 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -80 0.01 OUTPUT VOLTAGE (V p-p) TPC 9. Worst Harmonic vs. Output Voltage TPC 12. Open-Loop Gain and Phase vs. Frequency REV. C -7- PHASE (Degrees) 0 AD8042 10 8 6 VS = 5V G = +1 CL = 5pF RL = 2k TO 2.5V 60 55 T = +85 C G = -1 RL = 2k TO MIDPOINT CL = 5pF VS = 3V, 0.1% CLOSED-LOOP GAIN (dB) 50 T = +25 C SETTLING TIME (ns) 4 2 0 -2 -4 -6 -8 T = -40 C 45 VS = 3V, 1% 40 35 30 25 20 0.5 VS = +5V, 1% VS = 5V, 1% 2 VS = +5V, 0.1% VS = 5V, 0.1% -10 1 10 FREQUENCY (MHz) 100 500 1 1.5 BIPOLAR INPUT STEP (V) TPC 13. Closed-Loop Frequency Response vs. Temperature TPC 16. Settling Time 12 10 8 G = +1 CL = 5pF RL = 2k VS = 3V RL AND CL TO 1.5V 0 TEST CIRCUIT: 1.02k 1.02k OUT Vs = 5V COMMON-MODE REJECTION (dB) CLOSED-LOOP GAIN (dB) 6 4 2 0 -2 -4 -6 -8 1 VS = 5V RL AND CL TO 2.5V VS = 5V -10 -20 -30 -40 -50 -60 -70 -80 1.02k INCM 1.02k 10 FREQUENCY (MHz) 100 500 -90 10k 100k 1M 10M FREQUENCY (Hz) 100M 500M TPC 14. Closed-Loop Frequency Response vs. Supply TPC 17. CMRR vs. Frequency 0.80 100 OUTPUT SATURATION VOLTAGE (V) VS = +5V 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0 +5V - VOH (+125 C) +5V - VOH (+25 C) +5V - VOH (-55 C) OUTPUT RESISTANCE ( ) RBT = 50 10 VS = 5V G = +1 RBT = 0 1 RBT VOUT 0.1 +VOL (+125 C) +VOL (+25 C) +VOL (-55 C) 0.01 0.01 0.1 1 10 FREQUENCY (MHz) 100 500 0 5 10 15 20 25 30 35 LOAD CURRENT (mA) 40 45 50 TPC 15. Output Resistance vs. Frequency TPC 18. Output Saturation Voltage vs. Load Current -8- REV. C AD8042 12.0 VS = 11.5 5V 50 VS = +5V VOUT = 100mV STEP 40 SUPPLY CURRENT (mA) 11.0 10.5 10.0 9.5 9.0 % OVERSHOOT VS = +5V VS = +3V G = +2 30 20 G = +3 10 8.5 8.0 -40 -30 -20 -10 0 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 160 180 200 TEMPERATURE ( C) LOAD CAPACITANCE (pF) TPC 19. Supply Current vs. Temperature TPC 22. % Overshoot vs. Load Capacitance 6 0 -10 VS = +5V 5 4 VS = +5V RF = 2k RL = 2k TO +2.5V NORMALIZED GAIN (dB) -20 3 G = +2 2 1 0 -1 G = +10 -2 G = +5 -3 -4 1 10 FREQUENCY (MHz) 100 500 G = +2 RF = 200 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 10k 100k 1M 10M FREQUENCY (Hz) 100M 500M -PSRR +PSRR TPC 20. PSRR vs. Frequency TPC 23. Frequency Response vs. Closed-Loop Gain 10 9 8 VS = 5V RL = 2k G = -1 -10 -20 -30 -40 CROSSTALK (dB) OUTPUT VOLTAGE (V p-p) VS = +5V VIN = 0.6V p-p G = +2 RF = 1k VOUT 1 VOUT 2 VOUT 1 VOUT 2 , RL = 150 , RL = 1k TO +2.5V TO +2.5V 7 6 5 4 3 2 1 0 0.1 1.0 10.0 FREQUENCY (MHz) 100.0 -50 -60 -70 -80 -90 -100 -110 0.1 VOUT2 VOUT1 VOUT2 VOUT1 1 , RL = 1k , RL = 150 TO +2.5V TO +2.5V 100 200 10 FREQUENCY (MHz) TPC 21. Output Voltage Swing vs. Frequency TPC 24. Crosstalk (Output-to-Output) vs. Frequency REV. C -9- AD8042 5V 4.770V 4V VS = +5V G = -1 RL = 150 +2.6V TO +2.5V AV = +1 VS = +5V VIN = 100mV p-p RL = 1k TO 2.5V CL = 5pF 3V +2.5V 2V 1V 0.160V 0.5V 0V 200 s +2.4V 25mV 10ns TPC 25a. Output Swing with Load Reference to Supply Midpoint TPC 27. 100 mV Pulse Response, VS = +5 V 5V VS= +5V G = -1 RL= 150 TO GND G = -1 RL = 2k 3V TO +1.5V 4V 4.59V 3V 1.5V 2V 1V 0.5V 0V 0V 0.035V 200 s 0.5V 1s TPC 25b. Output Swing with Load Reference to Negative to Supply TPC 28. Rail-to-Rail Output Swing, VS = +3 V 4.5V 3.5V AV = +2 VS = +5V CL = 5pF RL = 1k TO +2.5V VIN = 1V p-p +1.6V VIN = 100mV p-p RL = 1k VS = +3V CL = 5pF AV = +1V TO 1.5V 2.5V +1.5V 1.5V +1.4V 0.5V 0.5V 10ns 25mV 10ns TPC 26. One Volt Pulse Response, VS = +5 V TPC 29. 100 mV Pulse Response, VS = +3 V -10- REV. C AD8042 OVERDRIVE RECOVERY Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 4, the AD8042 recovers within 30 ns from negative overdrive and within 25 ns from positive overdrive. Biasing of Q8 and Q36 is accomplished by I8 and I5, along with a common-mode feedback loop (not shown). This circuit topology allows the AD8042 to drive 40 mA of output current with the outputs within 0.5 V of the supply rails. On the input side, the device can handle voltages from 0.2 V below the negative rail to within 1.2 V of the positive rail. Exceeding these values will not cause phase reversal; however, the input ESD devices will begin to conduct if the input voltages exceed the rails by greater than 0.5 V. DRIVING CAPACITIVE LOADS +5V +2.5V 0V 1V VS = +5V VIN= +5V p-p G = +2 RL = 1k TO +2.5V 50ns Figure 4. Overdrive Recovery CIRCUIT DESCRIPTION The capacitive load drive of the AD8042 can be increased by adding a low valued resistor in series with the load. Figure 6 shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor with lower closed-loop gains accomplishes this same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and capacitive load. 1000 VS = 5V 200mV STEP WITH 30% OVERSHOOT RS = 5 CL 100 RS = 0 The AD8042 is fabricated on Analog Devices' proprietary eXtra-Fast Complementary Bipolar (XFCB) process which enables the construction of PNP and NPN transistors with similar fTs in the 2 GHz to 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 5). The smaller signal swings required on the first stage outputs (nodes S1P, S1N) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design harmonic distortion of better than -77 dB @ 1 MHz into 100 W with VOUT = 2 V p-p (Gain = +2) on a single 5 V supply is achieved. VCC I1 R26 Q4 R15 R2 VINP VINN SIP Q2 Q3 C7 VEE R5 R21 R3 SIN Q11 Q24 I7 Q47 I8 VCC Q13 Q17 Q40 VEE Q22 Q7 Q21 Q27 C9 R23 R27 Q31 C3 VOUT I10 R39 Q5 I2 I 3 Q25 Q51 Q50 Q39 Q23 I9 Q36 I5 VEE CAPACITIVE LOAD (pF) RS RS = 20 10 1 2 3 4 CLOSED-LOOP GAIN (V/V) 5 Figure 6. Capacitive Load Drive vs. Closed-Loop Gain Single-Supply Composite Video Line Driver The two op amps of an AD8042 can be configured as a singlesupply dual line driver for composite video. The wide signal swing of the AD8042 enables this function to be performed without using any type of clamping or dc restore circuit which can cause signal distortion. Figure 7 shows a schematic for a circuit that is driven by a single composite video source that is ac coupled, level shifted and applied to both + inputs of the two amplifiers. Each op amp provides a separate 75 W composite video output. To obtain single-supply operation, ac coupling is used throughout. The large capacitor values are required to ensure that there is minimal tilting of the video signals due to their low frequency (30 Hz) signal content. The circuit shown was measured to have a differential gain of 0.06% and a differential phase of 0.06. The input is terminated in 75 W and ac coupled via CIN to a voltage divider that provides the dc bias point to the input. Setting the optimal bias point requires some understanding of the nature of composite video signals and the video performance of the AD8042. Q8 Figure 5. AD8042 Simplified Schematic The AD8042's rail-to-rail output range is provided by a complementary common-emitter output stage. High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. REV. C -11- AD8042 +5V 4.99k 0.1F 4.99k COMPOSITE VIDEO IN 75 10k 10 F 3 2 RF 1k RG 1k 220 F 5 7 6 4 0.1 F RG 1k 220 F RF 1k RT 75 RL 75 1000 F VOUT 8 1 1000 F RT 75 0.1 F 10 F 75 COAX VOUT RL 75 To test this, the differential gain and differential phase were measured for the AD8042 while the supplies were varied. As the lower supply is raised to approach the video signal, the first effect to be observed is that the sync tips become compressed before the differential gain and differential phase are adversely affected. Thus, there must be adequate swing in the negative direction to pass the sync tips without compression. As the upper supply is lowered to approach the video, the differential gain and differential phase were not significantly adversely affected until the difference between the peak video output and the supply reached 0.6 V. Thus, the highest video level should be kept at least 0.6 V below the positive supply rail. Taking the above into account, it was found that the optimal point to bias the noninverting input is at 2.2 V dc. Operating at this point, the worst-case differential gain is measured at 0.06% and the worst-case differential phase is 0.06. The ac-coupling capacitors used in the circuit at first glance appear quite large. A composite video signal has a lower frequency band edge of 30 Hz. The resistances at the various ac coupling points--especially at the output--are quite small. In order to minimize phase shifts and baseline tilt, the large value capacitors are required. For video system performance that is not to be of the highest quality, the value of these capacitors can be reduced by a factor of up to five with only a slightly observable change in the picture quality. Single-Ended-to-Differential Driver Figure 7. Single-Supply Composite Video Line Driver Using AD8042 Signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capability than their peak-topeak amplitude after ac coupling. As a worst case, the dynamic signal swing required will approach twice the peak-to-peak value. The two bounding cases are for a duty cycle that is mostly low, but occasionally goes high at a fraction of a percent duty cycle and vice versa. Composite video is not quite this demanding. One bounding extreme is for a signal that is mostly black for an entire frame, but has a white (full intensity), minimum width spike at least once per frame. The other extreme is for a video signal that is full white everywhere. The blanking intervals and sync tips of such a signal will have negative going excursions in compliance with composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at its highest level (white) for only about 75% of the time. As a result of the duty cycle variations between the two extremes presented above, a 1 V p-p composite video signal that is multiplied by a gain of two requires about 3.2 V p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary duty cycle without distortion. Some circuits use a sync tip clamp along with ac coupling to hold the sync tips at a relatively constant level in order to lower the amount of dynamic signal swing required. However, these circuits can have artifacts like sync tip compression unless they are driven by sources with very low output impedance. The AD8042 not only has ample signal swing capability to handle the dynamic range required without using a sync tip clamp, but also has good video specifications like differential gain and differential phase when buffering these signals in an ac-coupled configuration. Using a cross-coupled single-ended-to-differential converter, the AD8042 makes a good general purpose differential line driver. This can be used for applications such as driving category 5 twisted pair wire which is becoming common for data communications in buildings. Figure 8 shows a configuration for a circuit that performs this function that can be used for video transmission over a differential pair or various data communication purposes. +5V 0.1 F RIN 1k 49.9 10 F VIN 3 8 2 AMP1 RA 1k RF 1 1k 60.4 50m RB 1k 121 VOUT AD8042 RB 1k RA 1k 6 5 AMP2 4 100 -5V 7 60.4 0.1 F 10 F Figure 8. Single-Ended-to-Differential Twisted Pair Line Driver -12- REV. C AD8042 Each of the AD8042's op amps is configured as a unity gain follower by the feedback resistors (RA). Each op amp output also drives the other as a unity gain inverter via the two RBS, creating a totally symmetrical circuit. 0.1 F +5V +5V 0.1 F If the + input to Amp 2 is grounded and a small positive signal is applied to the + input of Amp 1, the output of Amp 1 will be driven to saturation in the positive direction and the input of Amp 2 driven to saturation in the negative direction. This is similar to the way a conventional op amp behaves without any feedback. If a resistor (RF) is connected from the output of Amp 2 to the + input of Amp 1, negative feedback is provided which closes the loop. An input resistor (RI) will make the circuit look like a conventional inverting op amp configuration with differential outputs. The gain of this circuit from input to either output will be RF/ RI. Or the single-ended-to-differential gain will be 2 RF/RI. This gives the circuit the advantage of being able to adjust its gain by changing a single resistor. The cable has a characteristic impedance of about 120 W. Each driver output is back terminated with a pair of 60.4 W resistors to make the source look like 120 W. The receive end is terminated with 121 W, and the signal is measured differentially with a pair of scope probes. One channel on the oscilloscope is inverted and then the signals are added. The scope photo in Figure 9 shows a 10 MHz, 2 V p-p input signal driving the circuit with 50 m of category 5 twisted pair wire. VIN 1k 3 2 8 1k 1 +5V +5V 0.1 F 1k 28 DVDD 15 AVDD +5V 0.1 F 26 AVDD 14 OTR 13 BIT1 12 BIT2 11 BIT3 10 BIT4 9 BIT5 8 BIT6 7 BIT7 6 BIT8 5 BIT9 4 BIT10 3 BIT11 2 BIT12 0.1 F 1k AD8042 +5V 1k 6 2.49k 5 1k 7 4 VINA VINB CAPT 2.49k 0.1 F 0.1 F 10/16 0.1 F 0.1 F 18 17 22 AD9220 CAPB VREF SENSE CML 0.1 F CLOCK 1 CLK REFCOM 19 27 25 DVSS AVSS AVSS 16 Figure 10. AD8042 Differential Driver for the AD9220 12-Bit, 10-MSPS A/D Converter The circuit was tested with a 1 MHz input signal and clocked at 10 MHz. An FFT response of the digital output is shown in Figure 11. Pin 5 is biased at 2.5 V by the voltage divider and bypassed. This biases each output at 2.5 V. VIN is ac coupled such that VIN going positive makes VINA go positive and VINB go in the negative direction. The opposite happens for a negative going VIN. 1 1V 100 200mV 50ns VIN 90 10 0% 200mV VERTICAL SCALE (15dB/DIV) VOUT 9 2 8 3 7 6 4 5 Figure 9. Differential Driver Frequency Response Single-Supply Differential A/D Driver The single-ended-to-differential converter circuit is also useful as a differential driver for video speed, single-ended, differential input A/D converters. Figure 10 is a schematic that shows such a circuit differentially driving an AD9220, a 12-bit, 10-MSPS A/D converter. FUND FRQ 1000977 SMPL FRQ 10000000 THD SNR SINAD SFDR -82.00 71.13 70.79 -86.74 HARMONICS (dBc) 2nd -88.34 6th -99.47 3rd -86.74 7th -91.16 4th -99.26 8th -97.25 5th -90.67 9th -91.61 Figure 11. FFT of AD9220 Output When Driven by AD8042 REV. C -13- AD8042 HDSL Line Driver LAYOUT CONSIDERATIONS HDSL or high-bit-rate digital subscriber line is becoming popular as a means to provide data communication at DS1 rates (1.544 MBPS) over moderate distances via conventional telephone twisted pair wires. In these systems, the transceiver at the customer's end is sometimes powered via the twisted pair from a power source at the central office. It is sometimes required to raise the dc voltage of the power source to compensate for IR drops in long lines or lines with narrow gauge wires. Because of this, it is highly desirable to keep the power consumption of the customer's transceiver as low as possible. One means to realize significant power savings is to run the transceiver from a 5 V supply instead of the more conventional 12 V. The high output swing and current drive capability of the AD8042 make it ideally suited to this application. Figure 12 shows a circuit for the analog portion of an HDSL transceiver using the AD8042 as the line driver. 2k 6 232 VIN 2k 2 3 0.001 F 5 3k 7 ATT 2718AF 93DJ39 1 4 The specified high speed performance of the AD8042 requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce the stray capacitance. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other within 1/8 inch of each power pin. An additional large (0.47 mF-10 mF) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about one inch). These should be designed with a characteristic impedance of 50 W or 75 W and be properly terminated at each end. VOUT 1/2 AD8042 3k 10 1 5 1/2 AD8042 912 0.0027 F 2 7 9 34 2k 2 2k 6 2k 249 VREC 1 3 2k 2k 0.001 F 1/4 AD8044 Figure 12. HDSL Line Driver -14- REV. C AD8042 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) MIN SEATING PLANE 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 0.100 (2.54) BSC 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.17 (0.0067) 0.50 (0.0196) 0.25 (0.0099) 45 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 8/04--Data Sheet changed from REV. B to REV. C. Page Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7/02--Data Sheet changed from REV. A to REV. B. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 REV. C -15- -16- C01059-0-8/04(C) |
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